The present invention concerns the field of flip-flop design and pertains particularly to a flip-flop with a scan output designed for increased versatility.
Testing is an integral part in the designing and manufacturing devices such as integrated circuits. Testing may be performed by placing test vectors within internal registers of device. The resulting values the device places on its outputs are then monitored to verify proper functioning.
Special flip-flops, called scan flip-flops, may be used to form the internal registers used for testing. For example, scan flip-flops can have multiplexed inputs. This allows the scan flip-flops to receive input from one source during normal operation and from another source during testing.
Scan flip-flops may also employ separate scan-outputs which switch in conjunction with the Q outputs. This allows testing to occur with a minimum impact on normal operation of the circuit. See, for example, U.S. Pat. No. 5,043,986 issued to Vishwani D. Agrawal et al for Method and Integrated Circuit Adapted for Partial-Scan Testability; U.S. Pat. No. 5,175,447 issued to Soichi Kawasaki et al for Multifunctional Scan Flip-Flop; and U.S. Pat. No. 4,495,629 issued to John J. Zasio et al for CMOS Scannable Latch.